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HP 83434A 10 Gb/s 光波接收機

 租售83434A,維修83434A,83434A回購利用,83434A深圳市美佳特科技有限公司技術方案支持

描述

Keysight 83434A 接收機提供了*的光接口，使用戶可對 10 Gb/s SONET/SDH 和 IP 光網絡所使用的 10 Gb/s 光發射機進行比特誤碼率測試。

The Agilent 83434A 10 Gb/s lightwave receiver is designed to recover clock data and to provide linear, non-retimed data from digitally modulated SDH/ SONET STM-64/OC-192 optical signals, as well as signals employing forward error correction (FEC) at 10.664 Gb/s (option 106). 

The receiver is based on an amplified PIN receiver to produce a linear output with AGC stabilization. The receiver is designed to provide –16 dBm sensitivity with PRBS lengths to 231 –1 with BER performance of at least 1E-10. The recovered clock can be used as a trigger input for the Agilent Infiniium DCA to allow optical eye diagram measurements when no external clock signal is available for triggering.

 The recovered clock also provides the required clock input for the error detector of the Agilent 71612B error performance analyzer. The non-retimed data output can be used with an error detector to measure and optimize BER. 

The output of the receiver is also appropriate for eye contour and Q-factor measurements. The Agilent 83434A can be combined with the Agilent 83433A 10 Gb/s lightwave transmitter to create a complete optical link for system or fiber testing, or to form a basis for substitution testing of commercial transmitters and receivers. 

Specifications. Optical Input; Wavelength: 1300 to 1600 nm. Optical input power: –16 to 0 dBm. Return loss: 28 dB minimum. “Loss of optical input” alarm threshold: –25 to –20 dBm. Maximum Safe Input Level; 

Optical input power: +7 dBm maximum. Data Output; 

Amplitude: 0.5 to 1.5 V pk-pk. Lower 3 dB frequency: 0.10 MHz.

 Upper 3 dB frequency: 6.5 GHz.

 Return loss: 9.5 dB minimum. Impedance: 50 ohm. Recovered Clock Output; Amplitude: 0.5 to 1. 5 V pk-pk. 

Frequency: 9953.26 to 9953.30 MHz; 9953.28 nominal. 

Frequency (opt. 106): 10664.03 to 10664.43 MHz; 

10664.23 nominal. Duty cycle: 45/55% maximum; 50/50% nominal. Clock to data alignment: ±25.12 ps maximum. 3 dB bandwidth: 8 to 12 MHz; 10 MHz nominal.

 Jitter generation: 2 ps rms maximum. 

Return loss: 12 dB minimum. Impedance: 50 ohm.

 Option 106 For FEC signals, substitutes clock recovery at 10.644 GHz.